Altium PIC Two-Layer PCB Design

I am working on a compact, two-layer board centered on a Microchip PIC MCU whose main job is signal processing. The design will operate in the medium-frequency band—anywhere between 1 MHz and 100 MHz—so trace length, impedance control, and a clean ground strategy are critical. Because the circuit mixes sensitive analog stages with fast digital logic, careful partitioning and filtering are expected right from the schematic.

Your task is to create the complete Altium Designer project, starting with the schematic capture and ending with ready-for-fab Gerbers. The board will host mixed-signal components: op-amps and low-noise filters on the analog side, the PIC and its peripherals on the digital side, plus the usual power-conditioning blocks. Keep the stack-up strictly to two copper layers and observe standard FR-4 rules; no buried vias or exotic materials are planned.

Deliverables
• Altium schematic and PCB files (.SchDoc, .PcbDoc, project file)
• Well-structured libraries for all custom footprints and symbols
• BOM in CSV or Excel, complete with manufacturer part numbers and tolerances
• Gerber, drill and pick-and-place output verified by the built-in CAM viewer
• A short design note explaining layer usage, ground strategy, and any frequency-specific considerations

Acceptance criteria
• All nets pass ERC/DRC in the latest Altium release
• Board outline respects the maximum 70 × 50 mm envelope I will supply after kickoff
• Signal lines supporting the 1–100 MHz range show no stub or impedance issues in the built-in simulator
• Mixed-signal partitioning follows good practice, with clear analog, digital, and power regions

If you have handled similar PIC-based, mixed-signal boards before, your insight on decoupling and ADC noise reduction will be especially valuable.