Advanced Analytical Model Development for TFETs Using Visual TCAD/Silvaco TCAD

1. Scope of Work & Detailed Technical Requirements
Objective 1: Analytical Model Development & TCAD Validation
• Mathematical & Physics Formulation:
o Formulate 2D/3D surface potential models using Poisson's equation (parabolic approximation, superposition, or evanescent mode method) with appropriate boundary conditions for multi-gate architectures (Double-Gate, Gate-All-Around and Junctionless Gate-All-Around).
o Calculate electric field distribution, potential profile, and energy band bending across the channel and tunneling junction.
o Implement Non-Local Band-to-Band Tunneling (BTBT) models (e.g., Kane's model, Wentzel-Kramers-Brillouin (WKB) approximation) to extract tunneling current.
o Formulate expressions for Key Performance Indicators (KPIs): Threshold Voltage, On-State Current, Off-State Current, Subthreshold Swing, and Ambipolar Current.
• TCAD Numerical Calibration:
o Build full 2D/3D numerical TCAD models in Silvaco ATLAS or Cogenda Visual TCAD.
o Enable critical physical models: Non-local BTBT, Bandgap Narrowing (BGN), Shockley-Read-Hall (SRH) recombination, Lombardi mobility/surface scattering, and quantum confinement corrections.
o Deliverable Requirement: Analytical results (executed via MATLAB/Python) must match TCAD simulation data across all operating regions with an absolute average error rate of (< 5%).
Objective 2: Gate Material & Oxide Engineering
• Gate Architecture & Work-Function Engineering:
o Model Dual-Material Gate (DMG) and Triple-Material Gate (TMG) multi-gate TFET structures.
o Analyze the effect of varying gate work functions on tunneling barrier width, peak electric field, and potential step profile.
o Evaluate suppression of ambipolar behavior at the drain end through work-function engineering.
• Dielectric & Stack Engineering:
o Evaluate high-k gate dielectrics versus standard SiO2
o Design gate-oxide stacks to minimize equivalent oxide thickness (EOT) while mitigating gate leakage.
• Performance Metrics Target:
o I_{on}/I_{off} ratio > 10^6
o Average Subthreshold Swing (SS_{avg}) < 60 \{ mV/decade} at room temperature (300{ K})
o Reduced Drain-Induced Barrier Lowering (DIBL) and minimized parasitic gate capacitance (C_{gs}, C_{gd}).
Objective 3: Novel Material Exploration & Optimization
• Material Selection & Heterojunction Design:
o Explore low-bandgap and high-carrier-mobility materials: III-V semiconductors (InGaAs, GaAs, InAs) or 2D materials ({MoS}_2, {WSe}_2, Black Phosphorus).
o Design heterojunction TFET structures (Type-II staggered or Type-III broken band alignment at the tunneling junction) to lower tunneling barrier height and increase I_{on}
o Optional: Investigate Ferroelectric material integration (Negative Capacitance TFET / NC-TFET) using {HZO}to achieve internal voltage amplification.
• Optimization Framework:
o Perform multi-objective optimization balancing carrier effective mass, bandgap, dielectric constant, and channel thickness.
o Provide trade-off plots (e.g.,I_{on}vs SS, I_{on}vs parasitic capacitance).
Objective 4: Verilog-A Compact Modeling & Circuit-Level Integration
• Compact Model Extraction:
o Convert the analytical equations into a standard Verilog-A model or construct an accurate TCAD-driven Lookup Table (LUT) macromodel.
o Include static (IV) and dynamic (CV) behavior suitable for SPICE-class simulators.
• Circuit-Level Simulations (Cadence Virtuoso / Spectre / HSPICE):
o Implement the Verilog-A TFET model into target circuit topologies:
a. Basic Logic Gates: Inverter, 2-input NAND, 2-input NOR.
b. Ring Oscillator: 5-stage or 7-stage ring oscillator to quantify propagation delay, oscillation frequency, and transient response.
c. Memory Cell: 6T SRAM cell to evaluate Read Static Noise Margin (SNM), Write Static Noise Margin (WSNM), hold margin, and leakage power.
• Circuit Benchmarking Metrics:
o Propagation Delay, Static Power Dissipation, Dynamic Power, Power-Delay Product (PDP), and Energy-Delay Product (EDP) under ultra-low voltage conditions.

2. Deliverables Matrix & File Formats
Phase 1: Mathematical & Analytical Model
Objective: Mathematical & Analytical Model
Required Output / Deliverable: Derivation documents, solved potential equations, script for I/V and C/V generation
Target Format: MATLAB scripts (.m), Python scripts (.py), PDF report
Phase 2: TCAD Baseline & Gate Engineering
Objective: TCAD Baseline & Gate Engineering
Required Output / Deliverable: Validated TCAD structure files, mesh scripts, parameter variation plots
Target Format: TCAD Deck (.cmd, .in), Structure files (.str, .grd)
Phase 3: Novel Material Optimization
Objective: Novel Material Optimization
Required Output / Deliverable: Comparative study report, band diagrams, optimized geometry specs
Target Format: PDF report, Raw data spreadsheets (.xlsx/.csv)
Phase 4: Compact Model & Circuit Benchmark
Objective: Compact Model & Circuit Benchmark
Required Output / Deliverable: Functional Verilog-A file, circuit schematics, simulation netlists, transient/AC/DC plots
Target Format: Verilog-A (.va), SPICE netlists (.sp/.cir/.scs), Waveforms