Low-Power AHB/APB Design Thesis Project

I am preparing my M.Tech thesis and need a complete, slightly innovative digital design project that targets AMBA, AHB and APB buses. The central objective is a measurable reduction in power consumption—ideally demonstrated through techniques such as clock gating, power gating, or any other well-reasoned low-power methodology you can justify.

What I expect from you:
• Synthesizable RTL (Verilog or VHDL) for an AHB–to–APB subsystem showcasing the chosen low-power scheme.
• A comparative simulation report (pre- vs. post-technique) highlighting the numerical drop in dynamic or static power; use any standard EDA flow—ModelSim/Questa + Synopsys or Cadence tools are fine.
• A concise thesis-ready document that explains the architecture, the implemented optimisation, testbench strategy, and the obtained results.
• One peer-reviewed base research paper that closely relates to your optimisation, cited inside the report to support the improved figures.
• All project files: RTL, testbenches, scripts, waveforms, power analysis reports, and a slide deck summarising the work.

Target timeline: everything should be in my hands within a month so I have time for internal reviews.

If you have previously validated low-power AMBA designs or can demonstrate shaving meaningful milliwatts off an AHB/APB subsystem, I’d like to see your approach.