ESP32-S3 Prototype PCB Layout Design

Job Title
Hardware Engineer Needed: ESP32-S3 Low-Power Audio Recorder PCB (Dual Variant Prototype Layout)

Job Description
I am looking for an experienced electronics design engineer to create a custom, compact PCB layout based on the ESP32-S3 microcontroller.
The target system is a battery-powered, offline audio data-logger intended to record sound locally to a microSD card during specific daily schedules and securely upload files to a remote server over Wi-Fi during a specific time window.
To optimize power consumption and sound performance, I require TWO (2) separate PCB layout variations based on the same core schematic template.

Scope of Work & Deliverables
The freelancer will provide full design files (EasyEDA Pro/KiCad) alongside two separate production packages completely optimized for automated JLCPCB SMT Assembly (including Gerbers, Drill files, BOM, and CPL/Pick-and-Place coordinates).

Common Core Specifications (Both Variants)
1. Microcontroller: ESP32-S3-WROOM-1-N16R8 module (16MB Flash, 8MB PSRAM).
2. Antenna Requirement: Must use the module version featuring a U.FL / IPEX external antenna connector (not an integrated PCB trace antenna).
3. Storage: Integrated push-push MicroSD/TF card slot wired via high-speed SPI routing.
4. Power Input: Dual paths: Primary USB-C port (5V input) and secondary breakout header pin inputs for 5V/GND.
5. Battery Path & Connector: Onboard 1.25mm pitch JST-PH vertical connector wired to accept large capacity 3.7V Lithium-Polymer cells (2500mAh to 6600mAh+).
6. Battery Polarity: Must strictly match the Adafruit Standard Polarity (Looking at the male PCB header face with the indexing slot facing UP: LEFT pin is VBAT+ / RIGHT pin is GND).
7. Power Protection & Charging: Integrated USB charging circuit (e.g., TP4056 profile) and full lithium protection circuitry (over-charge, over-discharge/low-voltage cutoff, and over-current protection) with a low-quiescent 3.3V LDO.

Microphone Variant Specifications
• Variant A (I2S Architecture): Houses exactly ONE (1) TDK InvenSense ICS-43434 digital I2S microphone.
• Variant B (for Deep Sleep capability) (Ultra-Low-Power PDM Architecture): Houses exactly ONE (1) Vesper VM3011-U1 digital PDM microphone (JLCPCB Part #C7149370). The VM3011's DOUT pin must route straight to an ESP32-S3 hardware RTC EXT0 GPIO pin (e.g., GPIO 4) to act as a system-wide hardware wakeup trigger from Deep Sleep. The I2C lines must also route to the MCU for threshold settings.
The software firmware must be/should be able to be configured to utilize the ESP32-S3's internal hardware PDM-to-PCM conversion matrix to record clean WAV files from the VM3011.

Component Optimization Note
To minimize factory assembly fees, you must prioritize components from the JLCPCB "Basic Parts" library for standard passives, regulators, and common chips where possible.

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Milestones:

• Milestone 1 (50% of budget): Delivery and approval of the complete circuit schematic block and initial 3D rendering layout.
• Milestone 2 (50% of budget): Final delivery of the Gerber, BOM, and CPL files checked cleanly against the JLCPCB design rules (DRC).

The final deliverable source project files must be provided natively in either EasyEDA Pro or KiCad, utilizing the factory's components database to ensure zero assembly layout mismatches at checkout.