Algorithmic Trading Developer for FPGA/HLS

HLS / FPGA Developer – Low-Latency Algorithmic Trading
We are looking for an experienced HLS / FPGA Developer to join our team and work on the development and hardware acceleration of high-performance stock trading strategies.
The ideal candidate should have strong hands-on experience in FPGA architecture, RTL design, HLS, high-speed interfaces, and low-latency data processing, with an interest in applying these skills to algorithmic trading.
Key Responsibilities
• Develop and optimize low-latency trading strategies and market-data processing pipelines on FPGA.
• Translate trading algorithms into efficient RTL/HLS implementations.
• Design and optimize FPGA architectures for ultra-low-latency and deterministic execution.
• Develop high-throughput streaming data paths for market data, signal generation, order processing, and trading logic.
• Work closely with software/quant developers to convert trading strategies into FPGA-accelerated implementations.
Required Technical Skills
FPGA / RTL / HLS
• Strong understanding of FPGA design methodology and digital design fundamentals.
• Hands-on experience with Verilog/SystemVerilog RTL design.
• Strong practical experience with High-Level Synthesis (HLS).
• Experience with pipelining, parallelism, loop optimization, memory architecture, and latency optimization.
• Understanding of FPGA timing closure, resource utilization, clock-domain crossing, and high-speed data paths.
FPGA Platforms
• Hands-on experience with AMD/Xilinx FPGAs.
• Hands-on experience with Intel/Altera FPGAs.
• Experience with Vivado/Vitis HLS and/or Intel Quartus/HLS tools.
Good to Have
• Experience with 10G/25G/40G/100G Ethernet.
• Experience with UDP/TCP or custom low-latency network protocols.
• Experience with hardware/software co-design.
Experience:
5+ years in FPGA/HLS development; strong candidates with exceptional hands-on experience will also be considered.
Location: Remote
Employment: Contract